The present invention relates to a frequency control apparatus, and more particularly to a frequency control apparatus which is capable of performing the pull-in operation for a reproduced signal from an optical disk.
Furthermore, the present invention relates to a digital signal playback or reproducing apparatus, and more particularly to a digital signal playback or reproducing apparatus which decodes a digital signal reproduced from a recording medium.
A recording medium, such as an optical disk, is capable of storing information in a highly densified manner. A reproducing or playback system for this kind of recording medium includes a phase-locked loop circuit (i.e., PLL circuit) to obtain the data from a reproduced signal at accurate time intervals in a phase-locked manner. However, the pull-in range of the PLL circuit is theoretically limited to a narrow range of xc2x15xcx9c6%. For actual signals, this range may be further reduced to xc2x13xcx9c5%. When the optical disk is used, the relative speed of the signal widely varies. Namely, the reproducing or playback speed is variable in a wide range from an ordinary speed to a high speed equivalent to 20 times the ordinary speed. Thus, to control the pull-in process, it is necessary to provide a frequency control apparatus in the PLL circuit.
Conventional frequency control apparatuses are roughly classified into three groups. A first conventional frequency control apparatus uses a sync signal interval. In this case, the sync signal includes a transitional length (i.e., length between adjacent transitions) pattern longer than a run length restriction of the data (as known in a DVD). The sync signal interval is detectable based on a detected longest transitional length. An EFM (eight to fourteen modulation) signal of a compact disk (CD) has a maximum transitional length appearing at a predetermined probability. Thus, it is possible to detect the maximum transitional length of the EFM signal. The interval of the sync signal or the maximum transitional length is countable by using a clock generated from a voltage-controlled oscillator. Based on the counted value, it is feasible to check whether or not the detected value is correct. However, the first conventional frequency control apparatus requires a relatively long time to complete the judgement as an error detecting cycle is equivalent to the interval of the sync signal.
A second conventional frequency control apparatus uses the maximum transitional length pattern itself to judge whether or not a correct zero-cross detection number is obtained at the maximum transitional period. The PLL circuit controls the pull-in process accurately up to the range of xc2x15xcx9c6%. However, the second conventional frequency control apparatus is the same as the first conventional frequency control apparatus in that a relatively long time is required to complete the judgement because of a long error detecting cycle equivalent to the sync signal interval.
Furthermore, a third conventional frequency control apparatus utilizes an average transitional length which is defined by a ratio of an average of transitional lengths to a master clock counter. FIG. 10 is a block diagram showing an example of the third conventional frequency control apparatus. A counter 1 counts a master clock supplied from an oscillator. A comparator 2 compares the count value sent from the counter 1 with a predetermined reference value 1. The reference value 1 is sufficiently longer than a maximum transitional length of a reproduced signal.
The comparator 2 produces a coincidence signal at predetermined intervals. The coincidence signal serves as a reset signal which is supplied to the counter 1 and a zero-cross detector 3. The zero-cross detector detects and makes a count of zero-cross every time the reproduced signal crosses a zero-level (threshold level) which is determined considering the reproduced signal.
The zero-cross detection detector outputs an accumulated count value as a cross count value. The cross count value is supplied to a subtracter 4. The subtracter 4 reduces a predetermined reference value 2 from the received cross count value. The reference value 2 represents the ideal number of transition calculated based on an average transitional length in relation to the length of the reference value 1. The difference signal produced from the subtracter 4 is supplied to an error judging circuit 5. The error judging circuit 5 produces an error signal corresponding to the inputted difference signal. The error signal is supplied to a loop filter in the PLL circuit which produces a clock for detecting the reproduced signal, thereby controlling its characteristics.
According to the third conventional frequency control apparatus, the zero-cross detector 3 is reset at predetermined intervals. The zero cross is detected at the predetermined intervals. This is effectively applied to a scrambled signal. The error judgement is feasible at the intervals shorter than the sync signal intervals. Thus, it becomes possible to realize a high-speed pull-in operation which is usable as a rough adjustment.
However, as the conventional frequency control apparatus shown in FIG. 10 performs the error judgement at the predetermined intervals of the absolute time, there is a possibility that the error judgement is useless when the rate of the reproduced signal is changed from the ordinary reproduced speed to a high-speed reproduced speed, or from one high-speed reproduced speed to another high-speed reproduced speed.
Furthermore, each of the above-described conventional frequency control apparatuses requires the conditions that the zero-cross threshold level (i.e., setting of the zero level) is ideal and the transitional length (i.e., zero cross) is correctly judged. However, a rewritable optical disk, such as magneto-optical disk or a phase change disk, or a write once or a read only optical disk produces a reproduced signal which is characterized in that a signal level reduces with increasing frequency as shown in FIG. 11. Thus, the reproduced signal has a waveform peak level varying in accordance with the signal frequency. Furthermore, the waveform becomes asymmetric in the up-and-down direction. On these media, the center level (i.e., zero level) varies largely. Especially, this tendency remarkably appears when the optical disk is used for high-density recording.
To solve this problem, an automatic threshold control (ATC) can be used to adjust the center level of the reproduced signal to an optimum zero level. However, the threshold level may be deviated during a converging process of the ATC or when the ATC is performed for a vertically asymmetric signal to equalize the zero level of the zero-cross detection to the center of a maximum amplitude of the signal.
For example, FIG. 12A shows a case where a reproduced signal al has a symmetric waveform in the up-and-down direction and the threshold level is set to an ideal level I. In this case, a correct decoding data a3 is obtained in synchronism with a bit clock a2. However, during the converging process of ATC, the threshold level deviates from the ideal position to a level II with respect to a reproduced signal by having a symmetric waveform in the up-and-down direction as shown in FIG. 12B. In this case, a decoding data b3 obtained in synchronism with a bit clock b2 differs from the correct decoding data a3.
Furthermore, FIG. 12C shows another case where a reproduced signal c1 has an asymmetric waveform in the up-and-down direction but the threshold level is set to an ideal level III. In this case, a correct decoding data c3 is obtained in synchronism with a bit clock c2. However, when the ATC is performed to equalize the threshold level to the center level IV of a maximum amplitude of an asymmetric reproduced signal d1, a decoding data d3 obtained in synchronism with a bit clock d2 differs from the correct data c3.
When the threshold level is deviated from the ideal position as shown in FIGS. 12B and 12D, it becomes impossible to correctly detect the inversion positions. The maximum transitional length involved in the sync signal cannot be accurately judged. As a result, the maximum transitional length is erroneously detected as a value longer than the correct value. Therefore, the above-described first and second conventional frequency control apparatuses may malfunction and, as a result, the convergence will be delayed.
Furthermore, in the above conditions shown in FIGS. 12B and 12D, the zero-cross count becomes an inaccurate value. According to the third conventional frequency control apparatus, the relative speed of the signal will be detected as an incorrect value which is lower than the correct value. This will force the PLL circuit to erroneously reduce the frequency of the bit clock produced from the voltage-controlled oscillator. The condition is further worsened. As a result, the convergence will be delayed.
Meanwhile, the digital signal is reproducible from the optical disk by using a playback or reproducing apparatus. The sensitivity of the optical disk may fluctuate. A semiconductor laser is subjected to aged deterioration. Thus, a recording signal waveform will fluctuate. The duty ratio of a reproduced signal will also fluctuate. It is therefore necessary to introduce the automatic threshold control (ATC) for adequately DC controlling the threshold level of a binary comparator of the reproduced signal or an automatic gain control (AGC) for controlling the amplitude of the reproduced signal to a constant value. Furthermore, a frequency control is feasible to adequately perform the pull-in operation of a phase-locked loop (PLL) circuit which obtains a bit clock from the reproduced signal.
According to the ATC, it is desirable to correctly set a threshold level to the center of the peak-to-peak value at a minimum transitional length (i.e., minimum run length), although it is practically difficult. Simply setting the threshold level to the mid level between the uppermost peak and the lowermost peak of the reproduced signal has been conventionally performed. It is also conventionally known to maintain the reproduced signal value to a constant level obtained at the preamble portion. Such conventional techniques encounter with the problem that an error margin becomes small with increasing densification of the digital signals stored in the optical disk. Especially, according to the optical disk, the center level of a reproduced signal tends to fluctuate. The reproduced signal has an asymmetric waveform in the up-and-down direction. Thus, the conventional ATC cannot adequately control the threshold level.
According to the AGC of a conventional digital signal reproducing apparatus, it is desirable to maintain the minimum transitional length to a constant level, although it is practically difficult. Simply maintaining the peak-to-peak value of the reproduced signal to a constant value has been conventionally performed. Hence, the conventional techniques encounter with the problem that an error margin becomes small with increasing densification of the digital signals stored in the optical disk. Especially, the minimum inversional transition is small in the level, and is therefore sensitively influenced by the intersymbol interference or the cross talk.
Furthermore, according to the frequency control of a conventional digital signal reproducing apparatus, it takes a long time to detect a frequency error. It is impossible to accurately perform the judgement before the ATC and the AGC converges. It takes a long time to converge the frequency control. According to the frequency control, an error judgement is performed based on the number of zero-cross of the reproduced signal within a predetermined time. However, the zero-crossing operation may not be accurately performed when the signal waveform is asymmetric in the up-and-down direction. In such a case, the zero-cross frequency will include an error. The error judgement is not accurately performed.
In this manner, the conventional digital signal reproducing apparatus basically performs the ATC, the AGC and the frequency control. However, these controls are mutually influenced. It is not guaranteed that the system always converges. It was necessary to adjust the loop characteristics. For this reason, the convergence time becomes long and the error rate is worsened when an irregular reproduced signal is received. In a worst case, the system will not converge.
In view of the foregoing problems, the present invention has an object to provide a frequency control apparatus which is capable of causing the PLL circuit to quickly accomplish the pull-in process so that the decoding data can be accurately obtained irrespective of the deviation of the threshold value.
The present invention has an object to provide a digital signal reproducing apparatus capable of quickly converging even when the reproduced signal is irregular.
Furthermore, the present invention has another object to provide a digital signal reproducing apparatus capable of properly performing the automatic threshold control, the automatic gain control, and the frequency control for the reproduced signal of a recording medium storing information in a highly densified manner.
To accomplish the above and other related objects, the present invention provides a first frequency control apparatus for controlling a pull-in process of a phase-locked loop circuit which outputs a signal for accurately obtaining the data from an inputted reproduced signal at predetermined time intervals in a phase-locked manner. The frequency control apparatus comprises n pieces of cross detectors having n pieces of threshold levels different from each other and smaller than a maximum amplitude of the inputted reproduced signal, wherein n is an integer equal to or larger than 3, each cross detector incrementing a count value in response to a change of the inputted reproduced signal across a threshold level of the each cross detector and outputting an accumulated count value as a cross count value. A counting means is provided for counting a bit clock. A reset means is provided for comparing each of the cross count values outputted from the n pieces of cross detectors with a common reference value and producing a reset signal when one of the cross count values agrees with the common reference value to reset all of the n pieces of cross detectors and the counting means. And, an error judging circuit detects a deviation of a count value of the counting means relative to a proper value and produces an error signal based on a detected deviation. The error signal is supplied to a loop filter in the phase-locked loop circuit.
According to the first frequency control apparatus, the bit cross count value is checked when the cross count value becomes the common reference value, and the error signal is generated based on a deviation of the bit clock count value relative to the proper value. Thus, it becomes possible to produce the error signal in accordance with a signal rate of the reproduced signal. Furthermore, by using a plurality of threshold values, it becomes possible to realize a frequency control without relying on the ATC for the reproduced signal.
The present invention provides a second frequency control apparatus for controlling a pull-in process of a phase-locked loop circuit which outputs a signal for accurately obtaining the data from an inputted reproduced signal at predetermined time intervals in a phase-locked manner. The second frequency control apparatus comprises n pieces of cross detectors having n pieces of threshold levels different from each other and smaller than a maximum amplitude of the inputted reproduced signal, wherein n is an integer equal to or larger than 3. Each cross detector increments a count value in response to a change of the inputted reproduced signal across a threshold level of the each cross detector and outputs an accumulated count value as a cross count value. Each cross detector outputs a transitional timing signal. There are n pieces of transitional length detectors. Each transitional length detector detects a maximum length between adjacent transitions based on the transitional timing signal produced from a corresponding one of the n pieces of cross detectors. A reset means is provided for comparing each of the cross count values outputted from the n pieces of cross detectors with a common reference value and for producing a reset signal when one of the cross count values agrees with the common reference value to reset all of the n pieces of cross detectors and the transitional length detectors. A selecting means is provided for selecting a maximum transitional length (maximum length between adjacent transitions) detected by the transitional length detector which receives the cross count value agreeing with the common reference value from one of the n pieces of cross detectors. And, a comparing circuit detects a deviation of the maximum transitional length selected by the selecting means relative to a proper value, and produces an error signal based on a detected deviation, and further outputs the error signal to a loop filter in the phase-locked loop circuit.
It is preferable that the n pieces of threshold levels are equally spaced to provide same clearances between two adjacent threshold levels, and the clearances is smaller than an amplitude at a minimum transitional length of said inputted reproduced signal. According to this arrangement, one of the n pieces of threshold levels always shows a correct zero cross value.
It is also preferable that the common reference value is equivalent to a proper zero-cross count value averaged during a time interval sufficiently longer than each transitional length, and the counting means is for setting an initial value equivalent to a proper bit clock count value when the zero-cross count value becomes a predetermined value. The counting means includes a down counter which decrements the count value in response to each entry of the bit clock.
Furthermore, to accomplish the above-described object, another aspect of the present invention provides a first digital signal reproducing apparatus comprising a control means for performing at least one of a DC control and a gain control. The DC control is performed to control the DC level of an inputted reproduced signal or to control the threshold levels based on a DC error signal. The gain control is performed to control the amplitude of the inputted reproduced signal or to control the threshold clearances (i.e., clearances between threshold levels) based on a gain error signal. A cross detecting section has three or more threshold levels different from each other and smaller than a maximum amplitude of the reproduced signal obtained from the control means. The cross detecting section increments a count value for each threshold level in response to a change of the reproduced signal across the each threshold level, and clears all of count values when the count value of any threshold level reaches a preset value. And, the cross detecting section restarts the increment operation of the count value for each threshold level in response to the change of the reproduced signal across the each threshold level. A phase-locked loop circuit generates a bit clock. And, an error detecting section generates at least one of the DC error signal and the gain error signal based on a relative relationship between the count values of the threshold levels at the time the count value of any threshold level reaches the preset value.
The error detecting section of the first digital signal reproducing apparatus generates the DC error signal so as to shift the DC level of the reproduced signal toward a threshold level corresponding to a smallest count value among the count values. And, the error detecting section is responsive to a first count value corresponding to a central threshold level and, when the first count value reaches the preset value, compares each of second count values other than the first count value with a predetermined value which is smaller than the first count value. The error detecting section generates the gain error signal to increase the gain in a case where the second count values are smaller than the predetermined value and to decrease the gain in a case where the second count values are larger than the predetermined value and smaller than the first count value.
It is preferable that the error detecting section further generates a frequency error signal for controlling a pull-in process in the phase-locked loop circuit based on a detected deviation of a bit clock count value relative to a proper value at the time the count value of any threshold level reaches the preset value.
Furthermore, to accomplish the above-described object, the present invention provides a second digital signal reproducing apparatus comprising a control means and a cross detecting section identical with those of the above-described first digital signal reproducing apparatus. The second digital signal reproducing apparatus further comprises an equalizer for equalizing a waveform of the reproduced signal obtained from the control means. An error detecting section generates at least one of the DC error signal and the gain error signal based on a relative relationship between the count values of the threshold levels at the time the count value of any threshold level reaches the preset value. A phase comparing means is provided for generating a phase error signal with respect to the reproduced signal outputted from the control means or a calculated signal derived from the reproduced signal. A loop filter receives the phase error signal. And, an oscillator receives an output signal of the loop filter as a control voltage and generates a bit clock.
The error detecting section of the second digital signal reproducing apparatus generates the DC error signal so as to shift the DC level of the reproduced signal toward a threshold level corresponding to a smallest count value among the count values. And, the error detecting section is responsive to a first count value corresponding to a central threshold level and, when the first count value reaches the preset value, compares each of second count values other than the first count value with a predetermined value which is smaller than the first count value. The error detecting section generates the gain error signal to increase the gain in a case where the second count values are smaller than the predetermined value and also to decrease the gain in a case where the second count values are larger than the predetermined value and smaller than the first count value.
It is preferable that the error detecting section further generates a frequency error signal for controlling the characteristics of the loop filter based on a detected deviation of a bit clock count value relative to a proper value at the time the count value of any threshold level reaches the preset value.
With this arrangement, the error detecting section commonly uses the cross count value of the cross detecting section for each of the ATC, the AGC and the frequency control. At least one of the DC error signal and the gain error signal, or the frequency error signal, is produced based on the relative relationship between the count values of the three or more threshold levels at the time the count value of any threshold level reaches the preset value. Hence, it becomes possible to perform at least one of the DC control (i.e., ATC) and the gain control (i.e., AGC) or the frequency control.
Moreover, the error detecting section does not produce the gain error signal when any one of the second count values reaches the preset value. This surely prevents the gain control from being erroneously performed due to undesirable drift of the DC level of the reproduced signal.